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ds07-12621-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit microcontrollers cmos f 2 mc-8fx mb95130mb series mb95136mb/f133mbs/f133nbs/f133jbs/f134mbs/f134nbs/f134jbs/ mb95 f136mbs/f136nbs/f136jbs/f133mbw/f133nbw/f133jbw/f134mbw/ mb95 f134nbw/f134jbw/f136mbw/f136nbw/f136jbw/fv100d-103 description the mb95130mb series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. features ? f 2 mc-8fx cpu core instruction set optimized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock (for dual clock product) sub pll clock (for dual clock product) (continued)
mb95130mb series 2 (continued) ? timer 8/16-bit compound timer 1 channel 8/16-bit ppg 1 channel 16-bit ppg 1 channel timebase timer 1 channel watch prescaler (for dual clock product) 1 channel ? lin-uart 1 channel lin function, clock asynchronous (uart) or cloc k synchronous (sio) serial data transfer capable full duplex double buffer ? uart/sio 1 channel clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable full duplex double buffer ? external interrupt 8 channels interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8 channels 8-bit or 10-bit resolution can be selected. ? low-power consumption (standby) mode stop mode sleep mode watch mode (for dual clock product) timebase timer mode ? i/o port the number of maximum ports ? single clock product : 20 ports ? dual clock product : 18 ports configuration ? general-purpose i/o ports (coms) : single clock product : 20 ports dual clock product : 18 ports ? programmable input voltage levels of port automotive input level / cmos input level / hysteresis input level ? flash memory security function protects the content of flash memo ry (flash memory device only)
mb95130mb series 3 memory lineup flash memory ram mb95f133mbs/f133nbs/f133jbs 8 kbytes 256 bytes mb95f133mbw/f133nbw/f133jbw mb95f134mbs/f134nbs/f134jbs 16 kbytes 512 bytes mb95f134mbw/f134nbw/f134jbw mb95f136mbs/f136nbs/f136jbs 32 kbytes 1 kbyte mb95f136mbw/f136nbw/f136jbw
mb95130mb series 4 product lineup (continued) part number parameter mb95136mb mb95 f133mbs/ f134mbs/ f136mbs mb95 f133nbs/ f134nbs/ f136nbs mb95 f133mbw/ f134mbw/ f136mbw mb95 f133nbw/ f134nbw/ f136nbw mb95 f133jbs/ f134jbs/ f136jbs mb95 f133jbw/ f134jbw/ f136jbw type mask rom product flash memory product rom capacity* 1 32 kbytes (max) ram capacity* 1 1 kbyte (max) reset output yes no option* 2 clock system selectable single/dual clock* 3 single clock dual clock single clock dual clock low voltage detection reset yes/no no yes no yes clock supervisor yes/no no yes cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) peripheral functions general- purpose i/o port ? single clock product : 20 ports ? dual clock product : 18 ports programmable input voltage levels of port : automotive input level / cmos input level / hysteresis input level timebase timer (1 channel) interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32 .8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz (f or dual clock product) : min 250 ms wild register capable of replacing 3 bytes of rom data uart/sio (1 channel) data transfer capable in uart/sio full duplex double buffer, variable data lengt h (5/6/7/8-bit), built-in baud rate generator nrz type transfer format, error detected function lsb-first or msb-first can be selected. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin-uart (1 channel) dedicated reload timer allowing a wide range of communication speeds to be set. full duplex double buffer. clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin functions available as the lin master or lin slave. 8/10-bit a/d converter (8 channels) 8-bit or 10-bit resolution can be selected.
mb95130mb series 5 (continued) *1 : for rom capacity and ram capacity, refer to ? memory lineup?. *2 : for details of option, refer to ? mask option?. *3 : specify clock mode when ordering mask rom. *4 : embedded algorithm is a trade ma rk of advanced micro devices inc. note : part number of evaluation product in mb95130mb series is mb95fv100d-103. when using it, the mcu boar d (MB2146-303A) is required. part number parameter mb95136mb mb95 f133mbs/ f134mbs/ f136mbs mb95 f133nbs/ f134nbs/ f136nbs mb95 f133mbw/ f134mbw/ f136mbw mb95 f133nbw/ f134nbw/ f136nbw mb95 f133jbs/ f134jbs/ f136jbs mb95 f133jbw/ f134jbw/ f136jbw peripheral functions 8/16-bit compound timer (1 channel) each channel of the timer can be used as ?8-bit timer x 2 channels? or ?16-bit timer x 1 channel?. built-in timer function, pwc function, pwm functi on, capture function and square wave-form output count clock: 7 internal clocks an d external clock can be selected. 16-bit ppg (1 channel) pwm mode or one-shot mode can be selected. counter operating clock: eight selectable clock sources support for external trigger start 8/16-bit ppg (1 channel) each channel of the ppg can be used as ?8-bit ppg x 2 channels? or ?16-bit ppg x 1 channel?. counter operating clock: eight selectable clock sources watch counter (for dual clock product) (1 channel) count clock : four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63. (capable of counting for 1 minute when selecting clock source 1 second and sett ing counter value to 60) watch prescaler (for dual clock product) (1 channel) four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (8 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected.) can be used to recover from standby modes. flash memory supports automatic programming, embedded algorithm tm * 4 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time : 20 years erase can be performed on each block block protection with external programming voltage flash security feature for protec ting the content of the flash (mb95f136mbs/f136nbs/f136j bs/f136mbw/f136nbw/f136jbw) standby mode sleep, stop, watch (for dual clock product), and timebase timer
mb95130mb series 6 oscillation stabilization wait time the initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. the maximum value is shown below. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 14 -2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) part number package mb95136mb mb95f133mbs mb95f133nbs mb95f134mbs mb95f134nbs mb95f136mbs mb95f136nbs mb95f133jbs mb95f134jbs mb95f136jbs mb95f133mbw mb95f133nbw mb95f134mbw mb95f134nbw mb95f136mbw mb95f136nbw mb95f133jbw mb95f134jbw mb95f136jbw mb95fv100d-103 fpt-28p-m17 fpt-30p-m02 bga-224p-m08
mb95130mb series 7 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only t he functions of the mb95130 mb series but also thos e of other products to support software development for multiple series and models of the f 2 mc-8fx. the i/o addresses for peripheral resources not used by the mb95130mb series are theref ore access-barred. read/write access to those access- barred addresses may cause peripheral resources suppos ed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to an odd-numbered- byte address in the prohibited areas (if such access is used, the address may be read or written unexpectedly) . also, as the read values of prohibited addresses on the evaluation product ar e different to the values on the flash memory and mask rom products, do not use th ese values in the software processing. the evaluation product does not support the functions of some bits in sing le-byte registers. read/write access to these bits does not cause hardware malfunctions. no particular precautions are required to the flash memory and mask rom products, as they have the identical read/write operation to the evaluation products. ? difference of memory spaces if the amount of memory on the evaluation product is di fferent from that of the flash memory or mask rom product, carefully check the differ ence in the amount of memory from the model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption ? the current consumption of flash memory product is greater th an for mask rom product. ? for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corr esponding products? and ? package dimension?. ? operating voltage the operating voltage is different among the eval uation, flash memory, and mask rom products. for details of the operating voltage, refer to ? electrical characteristics?. ? difference mod pins a pull-down resistor is provided for the mod pin of the mask rom product.
mb95130mb series 8 pin assignment (top view) (fpt-28p-m17) * : single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. p15 p14/ppg0 p13/trg0/adtg p12/uck0/ec0 p11/uo0 p10/ui0 p07/int07/an07 p06/int06/an06/to01 p01/int01/an01/ppg01 p00/int00/an00/ppg00 p05/int05/an05/to00 p04/int04/an04/sin p03/int03/an03/sot p02/int02/an02/sck p16 pf0 pf1 mod x0 x1 v ss v cc av cc av ss c pg2/x1a * pg1/x0a * rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sop-28
mb95130mb series 9 (top view) (fpt-30p-m02) * : single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p16 pf0 pf1 mod x0 x1 v ss v cc c pg2/x1a * pg1/x0a * rst av cc av ss p00/int00/an00/ppg00 p15 p14/ppg0 p13/trg0/adtg p12/uck0/ec0 nc p11/uo0 p10/ui0 p07/int07/an07 p06/int06/an06/to01 p05/int05/an05/to00 p04/int04/an04/sin nc p03/int03/an03/sot p02/int02/an02/sck p01/int01/an01/ppg01 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ssop-30
mb95130mb series 10 pin description (continued) pin no. pin name i/o circuit type* 3 function ssop* 1 sop* 2 1 1 p16 h general-purpose i/o port 22 pf0 k general-purpose i/o port for large current 33 pf1 4 4 mod b operating mode designation pin 55 x0 a main clock oscillation input pin 6 6 x1 main clock oscillation input/output pin 77 v ss ? power supply pin (gnd) 88 v cc ? power supply pin 99 c ? capacity connection pin 10 10 pg2/x1a h/a single clock product is general-purpose port (pg2) . dual clock product is sub clock i nput/output oscillation pin (32 khz) . 11 11 pg1/x0a single clock product is general-purpose port (pg1) . dual clock product is sub clock input oscillation pin (32 khz) . 12 12 rst b? reset pin 13 13 av cc ? a/d converter power supply pin 14 14 av ss ? a/d converter power supply pin (gnd) 15 15 p00/int00/ an00/ ppg00 d general-purpose i/o port shared with external interrupt i nput (int00), a/d converter analog input (an00) and 8/16-bit ppg ch.0 output (ppg00). 16 16 p01/int01/ an01/ ppg01 general-purpose i/o port shared with external interrupt i nput (int01), a/d converter analog input (an01) and 8/16-bit ppg ch.0 output (ppg01). 17 17 p02/int02/ an02/sck general-purpose i/o port shared with external interrupt i nput (int02), a/d converter analog input (an02) and lin-uart clock i/o (sck). 18 18 p03/int03/ an03/sot general-purpose i/o port shared with external interrupt i nput (int03), a/d converter analog input (an03) and lin-uart data output (sot). 20 19 p04/int04/ an04/sin e general-purpose i/o port shared with external interrupt i nput (int04), a/d converter analog input (an04) and lin-uart data input (sin). 21 20 p05/int05/ an05/to00 d general-purpose i/o port shared with external interrupt in put (int05 & int06), a/d converter analog input (an05 & an06) and 8/16-bit compound timer ch.0 output (to00 & to01). 22 21 p06/int06/ an06/to01 23 22 p07/int07/ an07 general-purpose i/o port shared with external interrupt input (int07) and a/d converter analog input (an07).
mb95130mb series 11 (continued) *1 : fpt-30p-m02 *2 : fpt-28p-m17 *3 : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* 3 function ssop* 1 sop* 2 24 23 p10/uio g general-purpose i/o port shared with uart/sio ch.0 data input (ui0) 25 24 p11/uo0 h general-purpose i/o port shared with uart/sio ch.0 data output (uo0) 27 25 p12/uck0/ ec0 general-purpose i/o port shared with uart/sio ch.0 clock i/o (uck0) and 8/16-bit compound timer ch.0 clock input (ec0) 28 26 p13/trg0/ adtg general-purpose i/o port shared with 16-bit ppg ch.0 trigge r input (trg0) and a/d converter trigger input (adtg) 29 27 p14/ppg0 general-purpose i/o port shared with 16-bit ppg ch.0 output (ppg0) 30 28 p15 general-purpose i/o port 19,26 ? nc ? internally connected pins. be sure to leave it open.
mb95130mb series 12 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance: approx. 1 m ? low-speed side feedback resistance: approx. 10 m ? b only for input hysteresis input only for mask rom product pull-down resistor available only to mask rom product b? hysteresis input only for mask rom product reset output d cmos output hysteresis input analog input pull-up control available automotive input x0 (x0a) x1 (x1a) n-ch standby control clock input r mode input n-ch reset input reset output r n-ch p-ch p-ch pull-up control a/d control digital output digital output analog input automotive input hysteresis input standby control external interrupt control
mb95130mb series 13 (continued) type circuit remarks e cmos output cmos input hysteresis input analog input pull-up control available automotive input g cmos output cmos input hysteresis input pull-up control available automotive input h cmos output hysteresis input pull-up control available automotive input k cmos output hysteresis input automotive input r n-ch p-ch p-ch pull-up control digital output digital output hysteresis input automotive input cmos input a/d control standby control external interrupt control analog input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input automotive input p-ch p-ch n-ch r pull-up control standby control digital output digital output hysteresis input automotive input p-ch n-ch standby control digital output digital output hysteresis input automotive inpu t
mb95130mb series 14 handling devices ? preventing latch-up care must be taken to ensure that maximum volt age ratings are not exceeded when the devices are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if voltage higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc ) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system power supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power supply volt age may cause a malfunction even within the guaranteed operating range of the v cc power supply voltage. for stabilization, in principle, keep the variation in v cc ripple (p-p value) in a commercial frequency range (50 / 60 hz) not to exceed 10 % of the standard v cc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mome ntary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from the sub clock mode or stop mode. pin connection ? treatment of unused pins leaving unused input pins unconnect ed can cause abnormal operation or latch-up, leading to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to the output mode and left open, or set to the input mode and treated the same as unused input pins. if there is any unused output pin, make it open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, all the pins must be connected to external power supply and a ground line to lower the electro-magnetic emis sion level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to co nform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device. ? mode pin (mod) connect the mode pin directly to v cc or v ss pins. to prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to v cc or v ss pins and to provide a low-impedance connection.
mb95130mb series 15 use a ceramic capacitor or a capacitor with equivalent frequency characteristics. a bypass capacitor of v cc pin must have a capacitance value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. ? analog power supply always set the same potential to av cc and v cc . when v cc > av cc , the current may flow through the an00 to an07 pins. ? nc pins any pins marked ?nc?(not connected) must be left open. c s c ? c pin connection diagram
mb95130mb series 16 programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information about applicable adapter mo dels and parallel programmers, contact the following: flash support group, inc. tel: + 81-53-428-8380 ? sector configuration the following table shows sector-specific addresses fo r data access by cpu and by the parallel programmer. ? programming method 1) set the type code of the parallel programmer to ?17237?. 2) load program data to pr ogrammer addresses 18000 h to 1ffff h . 3) write data with the parallel programmer. ? programming method 1) set the type code of the parallel programmer to ?17237?. 2) load program data to programmer addresses 1c000 h to 1ffff h . 3) write data with the parallel programmer. package applicable adapter model parallel programmers fpt-28p-m17 tef110-95f136hspf af9708 (since rev 02.43e ) af9709/b (since rev 02.43e ) fpt-30p-m02 tef110-95f136mb *: programmer addresses are corresponding to cp u addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* 32 kbytes 8000 h 18000 h ffff h 1ffff h ? mb95f136mbs/f136nbs/f136mbw/f136 nbw/f136jbs/f136jbw (32 kbytes) *: programmer addresses are corresponding to cp u addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* 16 kbytes c000 h 1c000 h ffff h 1ffff h ? mb95f134mbs/f134nbs/f134jbs/f134 mbw/f134nbw/f134jbw (16 kbytes)
mb95130mb series 17 ? programming method 1) set the type code of the parallel programmer to ?17237?. 2) load program data to pr ogrammer addresses 1e000 h to 1ffff h . 3) write data with the parallel programmer. *: programmer addresses are corresponding to cp u addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* 8 kbytes e000 h 1e000 h ffff h 1ffff h ? mb95f133mbs/f133nbs/f133jbs/f133 mbw/f133nbw/f133jbw (8 kbytes)
mb95130mb series 18 block diagram f 2 mc- 8 fx cpu uart/ s io 1 ch a nnel w a tch pre s c a ler rom 3 2 k b yte s ram 1 k b yte lin-uart 1 ch a nnel 8 /16- b it ppg 2 ch a nnel s r s t x0/x1 pg2/(x1a) * pg1/(x0a) * p00/int00 to p07/int07 (p00/ppg00) (p01/ppg01) (p05/to00) (p06/to01) (p12/ec0) pf0/pf1 (p02/ s ck) (p0 3 / s ot) (p04/ s in) p00/an00 to p07/an07 p10/u10 p11/uo0 p12/uck0 p14/ppg0 p15/p16 av cc av ss mod, v cc , v ss , c p1 3 /trg0/adtg *: single clock product is a general-purpose port, and dual clock product is a sub clock oscillation pin. reset control clock control watch counter external interrupt 8 channels port internal bus interrupt control wild register 8/16-bit compound timer 1 channel port other pins 8/10-bit a/d converter 8 channels 16-bit ppg 1 channel
mb95130mb series 19 cpu core 1. memory space memory space of the mb95130mb series is 64 kbytes a nd consists of i/o area, data area, and program area. the memory space includes special-purpose areas such as the general-purpose registers and vector table. memory map of the mb95130mb series is shown below. flash memory ram address #1 address #2 mb95f133mbs/f133nbs/f133jbs 8 kbytes 256 bytes 0180 h e000 h mb95f133mbw/f133nbw/f133jbw mb95f134mbs/f134nbs/f134jbs 16 kbytes 512 bytes 0280 h c000 h mb95f134mbw/f134nbw/f134jbw mb95f136mbs/f136nbs/f136jbs 32 kbytes 1 kbyte 0480 h 8000 h mb95f136mbw/f136nbw/f136jbw 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h extended i/o fl as h memory 60 k b yte s ram 3 .75 k b yte s mb95fv100d-10 3 i/o 0000 h 00 8 0 h 0100 h 0200 h 0f 8 0 h 1000 h ffff h fl as h memory mb95f1 33 mb s /f1 33 nb s /f1 33 jb s mb95f1 3 4mb s /f1 3 4nb s /f1 3 4jb s mb95f1 3 6mb s /f1 3 6nb s /f1 3 6jb s mb95f1 33 mbw/f1 33 nbw/f1 33 jbw mb95f1 3 4mbw/f1 3 4nbw/f1 3 4jbw mb95f1 3 6mbw/f1 3 6nbw/f1 3 6jbw i/o ram ram 1 k b yte extended i/o ma s k rom 3 2 k b yte s extended i/o 0000 h 00 8 0 h 0100 h 0200 h 04 8 0 h 0f 8 0 h 1000 h ffff h mb951 3 6mb i/o 8 000 h addre ss #1 addre ss #2 memory map register register access prohibited access prohibited access prohibited access prohibited register
mb95130mb series 20 2. register the mb95130mb series has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the dedicated registers are as include: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for us e as a condition code register (ccr). (refer to the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instructi on, the lower 1-byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower 1-byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit regi ster to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc al ah tl th ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 dp2 dp1 dp0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95130mb series 21 the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent types of instructio ns such as mov a and dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic oper ation results or transfer data content and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is cleared to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by these bits. il1 il0 interrupt level priority 00 0 high low (no interruption) 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?1? r4 r3 r2 r1 r0 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 a15 a14 a13 a12 a11 a10 a9 a8
mb95130mb series 22 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register bank s on the memory. 1-bank contains 8 registers. up to a total of 32 banks can be used on the mb95130mb series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 this address = 0100 h + 8 (rp) r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1f8 h 1ff h bank 31 bank 0 8-bit register bank configuration 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance.
mb95130mb series 23 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r/w xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h to 0027 h ? (disabled) ?? 0028 h pdrf port f data register r/w 00000000 b 0029 h ddrf port f direction register r/w 00000000 b 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h pul0 port 0 pull-up register r/w 00000000 b 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h to 0034 h ? (disabled) ?? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 cont rol status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 cont rol status register 1 ch.0 r/w 00000000 b 0038 h , 0039 h ? (disabled) ?? 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h to 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg control status re gister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg control status re gister (lower byte) ch.0 r/w 00000000 b
mb95130mb series 24 (continued) address register abbreviation register name r/w initial value 0044 h to 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit control register ch.0,ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit control register ch.2,ch.3 r/w 00000000 b 004a h eic20 external interrupt circuit control register ch.4,ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6,ch.7 r/w 00000000 b 004c h to 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communicat ion control register r/w 000000xx b 0056 h smc10 uart/sio serial mode cont rol register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode c ontrol register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data register (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b 0073 h swre0 flash memory sector writ ing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writ ing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address co mpare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b
mb95130mb series 25 (continued) address register abbreviation register name r/w initial value 0078 h ? (register bank pointer (rp) mirror of direct bank pointer (dp) ?? 0079 h ilr0 interrupt level setting register 0 r/w 11111111 b 007a h ilr1 interrupt level setting register 1 r/w 11111111 b 007b h ilr2 interrupt level setting register 2 r/w 11111111 b 007c h ilr3 interrupt level setting register 3 r/w 11111111 b 007d h ilr4 interrupt level setting register 4 r/w 11111111 b 007e h ilr5 interrupt level setting register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting re gister (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting re gister (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting re gister (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting re gister (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting re gister (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting re gister (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 control status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 control status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h to 0f9b h ? (disabled) ?? 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b 0fa0 h to 0fa3 h ? (disabled) ??
mb95130mb series 26 (continued) address register abbreviation register name r/w initial value 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h to 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter re gister (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter register (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer register (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer register (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer re gister (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer re gister (lower byte) ch.0 r/w 11111111 b 0fb0 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate gener ator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler selection register ch.0 r/w 00000000 b 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h to 0fc2 h ? (disabled) ?? 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b 0fc4 h to 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fe6 h ? (disabled) ?? 0fe7 h ilsr2 input level select register 2 (option) r/w 00000000 b 0fe8 h , 0fe9 h ? (disabled) ?? 0fea h csvcr clock supervisor control register r/w 00011100 b 0feb h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ??
mb95130mb series 27 ? r/w access symbols ? initial value symbols note : do not write to the ? (disabled) ?. re ading the ? (disabled) ? returns an undefined value. r/w : readable / writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95130mb series 28 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (higher) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] (unused) irq9 ffe8 h ffe9 h l09 [1 : 0] (unused) irq10 ffe6 h ffe7 h l10 [1 : 0] (unused) irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] (unused) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] (unused) irq16 ffda h ffdb h l16 [1 : 0] (unused) irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] (unused) irq21 ffd0 h ffd1 h l21 [1 : 0] (unused) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95130mb series 29 electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1 v cc av cc v ss ? 0.3 v ss + 6.0 v *2 input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 4 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 4 ?l? level maximum output current i ol1 ? 15 ma other than pf0, pf1 i ol2 15 pf0, pf1 ?l? level average current i olav1 ? 4 ma other than pf0, pf1 average output current = operating current operating ratio (1 pin) i olav2 12 pf0, pf1 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than pf0, pf1 i oh2 ? 15 pf0, pf1 ?h? level average current i ohav1 ? ? 4 ma other than pf0, pf1 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 pf0, pf1 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total number of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb95130mb series 30 *1: the parameter is based on av ss = v ss = 0.0 v. *2: apply equal potential to av cc and v cc . *3: v i and v o should not exceed vcc + 0.3 v. v i must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4: applicable pins: p10 to p15, pf0, pf1 (inapplicable pins: pg1, pg2) ? use within recommended operating conditions. ? use at dc voltage (current). ? + b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this affects other devices. ? note that if the + b signal is inputted when the microcontroller powe r supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pi ns other than the a/d input pins (l cd drive pins, etc.) cannot accept +b signal input. ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95130mb series 31 2. recommended operating conditions (av ss = v ss = 0.0 v) *1: the value varies dependi ng on the operating frequency. *2: the value is 2.88 v when the low-voltage detection reset is used. *3: use ceramic capacitor or a capacitor with equival ent frequency characteristics. a bypass capacitor of v cc pin must have a capacitance value higher than c s . for connection of smoothing capacitor c s , refer to the diagram below. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc , av cc 2.42* 2 5.5* 1 v at normal operation 2.3 5.5 holds condition in stop mode smoothing capacitor c s 0.1 1.0 f*3 operating temperature t a ? 40 + 85 c c c s ? c pin connection diagram
mb95130mb series 32 3. dc characteristics (v cc = = av cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi p04 (selectable in sin), p10 (selectable in ui0) ? 0.7 v cc ? v cc + 0.3 v hysteresis input v ihsi p00 to p07, p10 to p16, pf0, pf1, pg1, pg2 ? 0.8 v cc ? v cc + 0.3 v hysteresis input v iha p00 to p07, p10 to p16, pf0, pf1, pg1, pg2 ? 0.8 vcc ? v cc + 0.3 v pin input at selecting of automotive input level v ihm rst , mod ? 0.7 v cc ? v cc + 0.3 v cmos input (flash memory product) ? 0.8 v cc ? v cc + 0.3 v hysteresis input (mask rom product) ?l? level input voltage v il p04 (selectable in sin), p10 (selectable in ui0) ? v ss ? 0.3 ? 0.3 v cc v hysteresis input v ils p00 to p07, p10 to p16, pf0, pf1, pg1, pg2 ? v ss ? 0.3 ? 0.2 v cc v hysteresis input v ila p00 to p07, p10 to p16, pf0, pf1, pg1, pg2 ? v ss ? 0.3 ? 0.5 v cc v pin input at selecting of automotive input level v ilm rst , mod ? v ss ? 0.3 ? 0.3 v cc v cmos input (flash memory product) ? v ss ? 0.3 ? 0.2 v cc v hysteresis input (mask rom product) ?h? level output voltage v oh1 output pins other than pf0, pf1 i oh = ? 4.0 ma v cc ? 0.5 ?? v v oh2 pf0, pf1 i oh = ? 8.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol1 output pins other than pf0 to pf7, rst * 1 i ol = 4.0 ma ?? 0.4 v v ol2 pf0, pf1 i ol = 12 ma ?? 0.4 v
mb95130mb series 33 (v cc = av cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max input leakage current (hi-z out- put leakage current) i li p00 to p07, p10 to p16, pf0, pf1, pg1, pg2 0.0 v < v i < v cc ? 5 ? + 5 a when the pull-up prohibition setting pull-up resistor r pull p00 to p07, p10 to p16, pg1, pg2 v i = 0.0 v 25 50 100 k ? when the pull-up permission setting pull-down resistor r mod mod v i = v cc 50 100 200 k ? mask rom product only input capacity c in other than av cc , av ss , c, v cc and v ss f = 1 mhz ? 515pf power supply current* 2 i cc v cc (external clock operation) v cc = 5.5 v f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 9.5 12.5 ma flash memory product (at other than flash memory writing and erasing) ? 30 35 ma flash memory product (at flash memory writing and erasing) ? 7.2 9.5 ma mask rom product f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 15.2 20.0 ma flash memory product (at other than flash memory writing and erasing) ? 35.7 42.5 ma flash memory product (at flash memory writing and erasing) ? 11.6 15.2 ma mask rom product
mb95130mb series 34 (v cc = av cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* 2 i ccs v cc (external clock operation) v cc = 5.5 v f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 7.5 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 12.0 ma i ccl v cc = 5.5 v f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) , t a = + 25 c ? 45 100 a dual clock product only i ccls v cc = 5.5 v f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) , t a = + 25 c ? 10 81 a dual clock product only i cct v cc = 5.5 v f cl = 32 khz watch mode main stop mode t a = + 25 c ? 4.6 27 a dual clock product only i ccmpll v cc = 5.5 v f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 9.3 12.5 ma flash memory product ? 79.5ma mask rom product f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 14.9 20.0 ma flash memory product ? 11.2 15.2 ma mask rom product i ccspll v cc = 5.5 v f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 160 400 a dual clock product only
mb95130mb series 35 (continued) (v cc = av cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1: product without clock supervisor only *2: ? the power supply current is specified by the exter nal clock. when the low-voltage detection and clock supervisor options are selected, the consumption current values of both the low-voltage detection circuit (i lv d ) and the built-in cr oscillator (i csv ) must also be added to the power supply current value. ? refer to ?4. ac characteristics: (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics: (2 ) source clock/machine clock? for f mp and f mpl . parameter symbol pin name condition value unit remarks min typ max power supply current* 2 i cts v cc (external clock operation) v cc = 5.5 v f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.15 1.1 ma i cch v cc = 5.5 v sub stop mode t a = + 25 c ? 3.5 20.0 a main stop mode for single clock product i a av cc v cc = 5.5 v f ch = 16 mhz when a/d conver- sion is in operation ? 2.4 4.7 ma i ah v cc = 5.5 v f ch = 16 mhz when a/d conver- sion is stopped t a = + 25 c ? 15 a
mb95130mb series 36 4. ac characteristics (1) clock timing (v cc = 2.42 v to 5.0 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name condi- tion value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 3.00 ? 4.06 mhz main pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll v cc = 2.3 v to 3.6 v clock cycle time t hcyl x0, x1 61.5 ? 1000 ns when using main oscillation circuit 30.8 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub oscillation circuit input clock pulse width t wh1 t wl1 x0 61.5 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise/fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95130mb series 37 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 ? input wave form for using external clock (main clock) x0 x1 f ch x0 f ch x1 c1 c2 ? figure of main clock input port external connection when using crystal or ceramic oscillator when using external clock open microcontroller microcontroller t lcyl t wh2 t cr 0.2 v cc x0a 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl2 ? input wave form for using external clock (sub clock) x0a x1a f cl x0a f cl x1a c1 c2 ? figure of sub clock input port external connection when using crystal or ceramic oscillator when using external clock open microcontroller microcontroller
mb95130mb series 38 (2) source clock/machine clock (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock division ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machine clock division ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the source clock can be selected as follows. ? main clock divided by 2 ? pll multiplication of main clock (selec t from 1, 2, 2.5, 4 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 8.125 mhz, pll multiplied by 2 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.50 ? 16.25 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using sub clock machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock f ch (main oscillation) f cl (sub oscillation) divided by 2 main pll 1 2 2.5 4 divided by 2 sub pll 2 3 4 sclk (source clock) clock mode select bit (sycc: scs1, scs0) mclk (machine clock) division circuit 1 1/4 1/8 1/16 ? outline of clock generation block
mb95130mb series 39 ? operating voltage - operating frequency (when t a = ? 40 c to + 85 c) ? mb95f133mbs/f133nbs/f133jbs/f134mbs/ f134nbs/f134jbs/f136m bs/f136nbs/f136jbs/ mb95f133mbw/f133nbw/f133jbw/f134mbw /f134nbw/f134jbw/f136mbw/f136nbw/ mb95f136jbw ? operating voltage - operating frequency (when t a = + 5 c to + 35 c) ? mb95fv100d-103 16.25 mhz 0.5 mhz 2.42 3 mhz 5.5 1 3 1.072 khz 16. 38 4 khz 2.42 3 2 khz 5.5 10 mhz 3 .5 source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range 2.7 5.5 1 3 1.072 khz 16. 38 4 khz 2.7 3 2 khz 5.5 16.25 mhz 0.5 mhz 3 mhz 10 mhz 3 .5 source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range
mb95130mb series 40 ? main pll operation frequency [mhz] 16.25 16 15 12 10 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8 .125 10 [mhz] machine clock frequency (f mp ) source clock frequency (f sp ) 2.5 2 1 4
mb95130mb series 41 (3) external reset (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation start time of oscillator is the time that the amplitude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillato rs, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name value unit remarks min max rst ?l? level pulse width t rstl rst 2 t mclk * 1 ? ns at normal operation oscillation time of oscillator* 2 + 100 ? s at stop mode, sub clock mode, sub sleep mode & watch mode 100 ? s at timebase timer mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 100 s rst x0 ? at normal operation ? at stop mode, sub clock mode, sub sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95130mb series 42 (4) power-on reset (av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) note : complete the power-on process within t he selected oscillation stabilization wait time. note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, set the slope of rising with in 30 mv/ms as shown below. parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ?? 50 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode limiting the slope of rising within 30 mv/ms is recommended.
mb95130mb series 43 (5) peripheral input timing (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse t ilih int00 to int07, ec0, trg0/adtg 2 t mclk * ? ns peripheral input ?l? pulse t ihil 2 t mclk * ? ns t ilih int00 to int07, ec0,trg0/adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95130mb series 44 (6) uart/sio serial i/o timing (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1 ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v uck0 uo0 ui0 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v uck0 uo0 ui0 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95130mb series 45 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to dela y half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95130mb series 46 0.8 v 0.8 v 2.4 v t slovi t ivshi t shixi 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slove t ivshe t shixe 2.4 v 0.8 v t r t f sck sot sin t slsh t shsl 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95130mb series 47 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to dela y half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95130mb series 48 0.8 v 2.4 v 2.4 v t shovi t ivsli t slixi 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode 0.2 v cc 0.2 v cc t shove t ivsle t slixe 2.4 v 0.8 v t f t r sck sot sin t shsl t slsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc
mb95130mb series 49 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recepti on data is performed at risi ng edge or falling edge of the serial clock. *2 : serial clock delay function is used to del ay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 0.8 v 0.8 v t shovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovli t ivsli t slixi
mb95130mb series 50 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 5.0 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 2.4 v 0.8 v t slovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovhi t ivshi t shixi
mb95130mb series 51 (8) low voltage detection (av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol value unit remarks min typ max release voltage v dl + 2.52 2.70 2.88 v at power-supply rise detection voltage v dl ? 2.42 2.60 2.78 v at power-supply fall hysteresis width v hys 70 100 ? mv power-supply start voltage v off ?? 2.3 v power-supply end voltage v on 4.9 ?? v power-supply voltage change time (at power supply rise) t r 0.3 ?? s slope of power supply that reset re- lease signal generates ? 3000 ? s slope of power supply that reset re- lease signal generates within rating (v dl+ ) power-supply voltage change time (at power supply fall) t f 300 ?? s slope of power supply that reset detection signal generates ? 300 ? s slope of power supply that reset detection signal generates within rat- ing (v dl- ) reset release delay time t d1 ?? 400 s reset detection delay time t d2 ?? 30 s consumption current i lvd ? 38 50 a consumption current of low voltage detection circuit only
mb95130mb series 52 v hys t d2 t d1 t r t f v cc v cc v on v off v dl+ v dl- time internal reset signal time
mb95130mb series 53 (9) clock supervisor clock (v cc = av cc = 5 v 10 % , av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol value unit remarks min typ max oscillation frequency f out 50 100 200 khz oscillation start time t wk ?? 10 s current consumption i csv ? 20 36 a current consumption of built-in cr oscillator at 100 khz oscillation
mb95130mb series 54 5. a/d converter (1) a/d converter electrical characteristics (av cc = v cc = 4.0 v to 5.5 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v full-scale transition voltage v fst av cc ? 4.5 lsb av cc ? 1.5 lsb av cc + 0.5 lsb v compare time ? 0.9 ? 16500 s 4.5 v av cc 5.5 v 1.8 ? 16500 s 4.0 v av cc < 4.5 v sampling time ? 0.6 ? s 4.5 v avcc 5.5 v, at external impedance < at 5.4 k ? 1.2 ? s 4.0 v avcc 4.5 v, at external impedance < at 2.4 k ? analog input current i ain ? 0.3 ? + 0.3 a analog input voltage v ain av ss ? av cc v
mb95130mb series 55 (2) notes on using a/d converter ? external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exter nal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore to satisfy the a/d conversion precision standard , consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suff icient, connect a capacitor of about 0.1 f to the analog input pin. ? errors as |av cc ? av ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit rc 4.5 v av cc 5.5 v 2.0 k ? (max) 16 pf (max) 4.0 v av cc < 4.5 v 8.2 k ? (max) 16 pf (max) comparator during sampling : on 20 18 16 14 12 10 8 6 4 2 0 02 134 100 90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 (external impedance = at 0 k ? to 100 k ? ) (external impedance = at 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] av cc 4.0 v ? the relationship between external impedance and minimum sampling time av cc 4.5 v av cc 4.5 v av cc 4.0 v
mb95130mb series 56 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss av cc av ss v nt av cc {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = av cc ? av ss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : voltage at which digital output transits from (n-1) h to n h . =
mb95130mb series 57 (continued) v (n + 1) t ? v nt 1 lsb av ss av cc av ss av cc av ss av cc v nt av ss av cc 001 h 002 h 003 h 004 h 3fc h 3fd h 3fe h 3ff h 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h (n - 2) h (n - 1) h n h (n + 1) h {1 lsb n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristics actual conversion characteristics ideal characteristics analog input v fst (actual value) zero transition error digital output actual conversion characteristics actual conversion characteristics analog input v ot (actual value) ? 1 differential linear error of digital output n linear error of digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristics actual conversion characteristics analog input ideal characteristics differential linear error digital output actual conversion characteristics actual conversion characteristics analog input ideal characteristics v fst (actual value) v ot (actual value) n : a/d converter digital output value v nt : voltage at which digital output transits from (n - 1) h to n h . v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = av cc ? 1.5 lsb [v] ideal characteristics = =
mb95130mb series 58 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 5.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 4.5 v, 10000 cycles *3 : this value comes from the technology qualification (u sing arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max chip erase time ? 1.0* 1 15.0* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600 s excludes system-level overhead. erase/program cycle 10000 ?? cycle power supply voltage at erase/ program 4.5 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = + 85 c
mb95130mb series 59 mask option *: refer to table below about clock mode select, low volt age detection reset, clock s upervisor select and reset output. no. part number mb95136mb mb95f133mbs mb95f133nbs mb95f133jbs mb95f134mbs mb95f134nbs mb95f134jbs mb95f136mbs mb95f136nbs mb95f136jbs mb95f133mbw mb95f133nbw mb95f133jbw mb95f134mbw mb95f134nbw mb95f134jbw mb95f136mbw mb95f136nbw mb95f136jbw mb95fv100d-103 specifying procedure specify when ordering mask setting disabled setting disabled setting disabled 1 clock mode select ? single-system clock mode ? dual-system clock mode selectable single-system clock mode dual-system clock mode changing by the switch on mcu board 2 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset specify when ordering mask specified by part number specified by part number change by the switch on mcu board 3 clock supervisor* ? with clock supervisor ? without clock supervisor specify when ordering mask specified by part number specified by part number change by the switch on mcu board 4 reset output* ? with reset output ? without reset output specify when ordering mask specified by part number specified by part number mcu board switch set as following ; ? with supervisor : without reset output ? without supervisor : with reset output 5 oscillation stabilization wait time fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch
mb95130mb series 60 part number clock mode select low-voltage detection reset clock supervisor reset output mb95136mb single - system no no yes yes no yes yes yes no dual - system no no yes yes no yes yes yes no mb95f133mbs single - system no no yes mb95f133nbs yes no yes mb95f133jbs yes yes no mb95f134mbs no no yes mb95f134nbs yes no yes mb95f134jbs yes yes no mb95f136mbs no no yes mb95f136nbs yes no yes mb95f136jbs yes yes no mb95f133mbw dual - system no no yes mb95f133nbw yes no yes mb95f133jbw yes yes no mb95f134mbw no no yes mb95f134nbw yes no yes mb95f134jbw yes yes no mb95f136mbw no no yes mb95f136nbw yes no yes mb95f136jbw yes yes no mb95fv100d-103 single - system no no yes yes no yes yes yes no dual - system no no yes yes no yes yes yes no
mb95130mb series 61 ordering information part number package mb95136mbpf mb95f133mbspf mb95f133nbspf mb95f133jbspf mb95f134mbspf mb95f134nbspf mb95f134jbspf mb95f136mbspf mb95f136nbspf mb95f136jbspf mb95f133mbwpf mb95f133nbwpf mb95f133jbwpf mb95f134mbwpf mb95f134nbwpf mb95f134jbwpf mb95f136mbwpf mb95f136nbwpf mb95f136jbwpf 28-pin plastic sop (fpt-28p-m17) mb95136mbpfv mb95f133mbspfv mb95f133nbspfv mb95f133jbspfv mb95f134mbspfv mb95f134nbspfv mb95f134jbspfv mb95f136mbspfv mb95f136nbspfv mb95f136jbspfv mb95f133mbwpfv mb95f133nbwpfv mb95f133jbwpfv mb95f134mbwpfv mb95f134nbwpfv mb95f134jbwpfv mb95f136mbwpfv mb95f136nbwpfv mb95f136jbwpfv 30-pin plastic ssop (fpt-30p-m02) MB2146-303A (mb95fv100d-103pbt) mcu board ( ) 224-pin plastic pfbga (bga-224p-m08)
mb95130mb series 62 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 2 8 -pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 8 .6 17.75 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 2. 8 0 mm max weight 0. 8 2 g code (reference) p- s op2 8 - 8 .6 17.75-1.27 2 8 -pin pl as tic s op (fpt-2 8 p-m17) (fpt-2 8 p-m17) c 2002 fujit s u limited f2 8 04 8s -c- 3 -4 .699 ?.00 8 +.010 ?0.20 +0.25 17.75 1 1.27(.050) 8 .600.20 (. 33 9.00 8 ) 11. 8 00. 3 0 (.465.012) m 0.1 3 (.005) 14 15 2 8 0.10(.004) 0.470.0 8 (.019.00 3 ) index "a" ?0.04 +0.0 3 0.17 .007 +.001 ?.002 0~ 8 ? 0.25(.010) det a il s of "a" p a rt (mo u nting height) 2.650.15 (.104.006) 0.200.15 (.00 8 .006) ( s t a nd off) 0. 8 00.20 (.0 3 1.00 8 ) 0. 88 0.15 (.0 3 5.006) * 1 * 2 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * 1 : the s e dimen s ion s incl u de re s in protr us ion. note 2) * 2 : the s e dimen s ion s do not incl u de re s in protr us ion. note 3 )pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 4) pin s width do not incl u de tie ba r c u tting rem a inder.
mb95130mb series 63 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 3 0-pin pl as tic ss op le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 5.60 9.70 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.45 mm max code (reference) p- ss op 3 0-5.6 9.7-0.65 3 0-pin pl as tic ss op (fpt- 3 0p-m02) (fpt- 3 0p-m02) c 200 3 fujit s u limited f 3 000 3s -c- 3 -4 9.700.10(. 38 2.004) 5.600.10 7.600.20 (.220.004) (.299.00 8 ) "a" (.007.001) 0.170.0 3 .009 ?.00 3 +.00 3 ?0.07 +0.0 8 0.24 index * 1 * 2 0.25(.010) 0.100.10 (.004.004) ( s t a nd off) det a il s of "a" p a rt (mo u nting height) 1.25 +0.20 ?0.10 ?.004 +.00 8 .049 0~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.10(.004) 0.10(.004) 1 15 3 016 0.65(.026) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * 1 : re s in protr us ion. (e a ch s ide : +0.15 (.006) m a x). note 2) * 2 : the s e dimen s ion s do not incl u de re s in protr us ion. note 3 )pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 4) pin s width do not incl u de tie ba r c u tting rem a inder.
mb95130mb series f0707 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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